The advent of high-speed data communications has led to new protocols being developed that transfer data at high rates of speed. Ten Gigabit Ethernet is one such protocol. Ten Gigabit Ethernet has defined two interfaces between a physical layer device (PHY) and an Ethernet controller, also referred to as a media access controller (MAC). These two interfaces are a 10 Gigabit per second (Gbps) Attachment Unit Interface, also referred to as xe2x80x9cXAUI,xe2x80x9d and a 10 Gbps Media Independent Interface, also referred to as xe2x80x9cXGMII.xe2x80x9d
XGMII is a parallel interface consisting of 32 data lines, one clock line, and-four control lines in each direction. The clock runs at 156.25 megahertz and the data is clocked in and out on both the rising and falling edges of the clock. XAUI is a serial interface of four lanes of data that are 8 bit/10 bit (8 b/10 b) encoded. The encoding process takes the parallel data of XGMII and divides it into four lanes, each having 10 bits. Each lane runs at 3.125 Gigabaud in each direction. XAUI has no clock, because the clock signal is embedded in the data as part of the 8 b/10 b encoding.
XGMIII is designed to be a standard parallel digital interface between the MAC and the PHY, but it is difficult to implement on standard printed circuit board (PCB) material over nominal trace distances because it is a parallel bus operating at high speeds. The alternative serial interface, XAUI, was developed to allow the distance between the PHY and the MAC to be at least 20 inches of PCB trace.
Most chips having a MAC are digital chips and therefore have a XGMII interface. Thus, devices are needed to convert XGMII to XAUI. A representative example is the Intel LXT1001 chip. The LXT1001 chip is placed near 10 Gigabit MAC chips that have a XGMII interface. The Intel LXT1001 chip accepts parallel data from the XGMII, which provides 32 data signals, four control signals and a clock signal. The data is latched into four XGMII input buffers. The data from the XGMII input buffers is encoded by an 8 b/10 b encoder. The encoding ensures that sufficient transitions are embedded to allow the receiver to recover a clock from the serial bit data stream.
After encoding, the four streams of 8 b/10 b encoded characters are each transmitted to an XAUI transmitter. The XAUI transmitter includes a pre-transmit equalizer, a parallel-to-serial converter and an XAUI output buffer. For each data stream, the data bits are clocked in parallel from the equalizer to the parallel-to-serial converter, and transmitted in serial to the output buffer.
In a high-speed serial link application, circuit designers encounter the requirement to convert a n bit parallel data stream into bits in a serial datastream. A common method to implement this conversion is utilize a n-to-1 multiplexing scheme in which n gated switches are applied to allow n bits of data go through in sequence. The outputs of the n gated switches are tied together to go to a next stage, which is most often a buffer.
When data speeds reach the Gigahertz range, a simple complimentary metal oxide semiconductor (CMOS) transmission gate switch is not sufficient. Furthermore, because of the different response speeds of positive polarity metal oxide semiconductor (PMOS) and negative polarity metal oxide semiconductor (NMOS) (NMOS is utilized to pull down the clock transition from high to low and PMOS is utilized when the transition is from low to high), the rising and falling edges of the clock signal are often different and this difference translates into clock duty cycle distortion. This problem is worsened because PMOS and NMOS vary differently over process and temperature thresholds.
FIG. 1 illustrates a current mode logic (CML) cell in use in Gigahertz circuit applications according to the prior art. In Gigahertz applications, these switches are often CML cells as shown in FIG. 1. However, the utilization of CML cells introduces a circuit with low current efficiency, meaning these circuits have a high current consumption, which is a critical parameter in many applications.
FIG. 2 illustrates a block diagram of CML cells and the passage of data through the CML cells according to the prior art. Any of these n CML cells actually pass data for only 1/N of a clock cycle and sit idle for the remaining clock cycle time ((Nxe2x88x921)/N). During the idle time, the tail current of the CML cell is thrown away to the power supply.
FIG. 3 illustrates a circuit diagram of a conventional multiplex implementation of parallel-to-serial conversion according to the prior art. In this embodiment, the current branches are connected to the output load one at a time. In an embodiment where the parallel-to-serial conversion is a n bit to one bit conversion, the required tail current of each of the current branches be nxc3x97I0. In the conventional multiplex, only one of the branches is actively converting but all of the current sources are being utilized in a sequent fashion. Thus, the total current is nxc3x97nxc3x97I0.
Accordingly, a need exists for a parallel-to-serial conversion system that reduces current consumption by a significant factor.